Digital Logic Project

Automation System with Flip-Flops

Sequential control platform orchestrating industrial automation states through robust flip-flop logic and real-time visualization.

← Back to projects

Project Overview

The automation system coordinates a multi-stage assembly process using JK and D flip-flops to model state transitions. Coupled with 7-segment displays, the controller communicates machine status, validates inputs, and prevents unsafe states. The architecture emphasizes deterministic state flow, maintainability, and simple diagnostics for operators.

Key Features

  • Deterministic state machine driving actuators and safety interlocks.
  • Real-time fault detection with visual alerts on 7-segment indicators.
  • Modular input layer allowing easy addition of sensors or manual overrides.
  • Extensive simulation suite ensuring timing closure before deployment.

Gallery

Snapshots from prototyping and the final deployment dashboard.

Flip-flop automation state machine diagram
State machine diagram highlighting sequential transitions.
FPGA prototype of the automation system
FPGA prototype driving the automation test bench with live monitoring.

Challenges & Lessons Learned

  • Transitioned from combinational prototypes to synchronous logic, reinforcing the importance of debouncing and metastability mitigation.
  • Tuned flip-flop timing constraints to avoid setup/hold violations when interfacing with mechanical sensors.
  • Built reusable VHDL packages for state definitions, accelerating future automation projects.